Isep-Ieee Student Branch

Isep-Ieee Student Branch IEEE Institut Supérieur d'Electronique de Paris

19/12/2018

If there’s one thing I love about this job, it’s about finding what makes the companies in our industry tick. This goes above and beyond just the product announcements, the reviews, or user experiences: it pays off to take heed of what a company is saying, how they are saying it, and how people ...

The ISEP IEEE Student Branch, in association with IEEE CAS France cordially invites you to attend our CAS outreach 2015 ...
15/12/2015

The ISEP IEEE Student Branch, in association with IEEE CAS France cordially invites you to attend our CAS outreach 2015 talk on “Using Analog Design to Make Digital Better: Efficient RISC-V Processor in 28nm FDSOI ” by Prof. Borivoje Nikolić on Wednesday, 16th December, 2015 from 16:00 to 17:00. The talk will take place at 46 rue Barrault, 75634 Paris Cedex 13 – France, School of Institut Mines-Telecom. Participation for the event is free of charge with prior registration by sending an email to kshaik@ ieee.org. Please feel free to pass on this information in your contacts.
The talk will be followed by a networking reception sponsored by ISEP and IEEE France Section
For more information about the event, please contact – kshaikieee.org
Please find below the brief bio of our distinguished speaker.
Title: Using Analog Design to Make Digital Better: Efficient RISC-V Processor in 28nm FDSOI
Date: 16th December, 2015: 4 P.M to 5P.M.
Venue: 46 rue Barrault, 75634 Paris Cedex 13 – France, School of Institut Mines-Telecom
Abstract: This talk presents a design of an energy-efficient microprocessor that implements several techniques for operation in a very wide voltage range. A particular implementation is based on an open Berkeley RISC-V architecture. To enable agile dynamic voltage and frequency scaling, with high energy efficiency the design implements an integrated switched-capacitor DC-DC converter. A custom-designed SRAM-based cache operates in a wide 0.45-1V supply range. Techniques that enable low-voltage SRAM operation include 8T cells, assist techniques and differential read. Architectural resiliency techniques include the use of error correction and dynamic column redundancy. The processor is implemented by using an agile design methodology.
Bio: Prof. Borivoje Nikolić is the National Semiconductor Distinguished Professor of Engineering at the University of California, Berkeley. He received the Dipl.Ing. and M.Sc. degrees in electrical engineering from the University of Belgrade, Serbia, in 1992 and 1994, respectively, and the Ph.D. degree from the University of California at Davis in 1999. His research activities include digital, analog and RF integrated circuit design and VLSI implementation of communications and signal processing algorithms. He is co-author of the book Digital Integrated Circuits: A Design Perspective, 2nd ed, Prentice-Hall, 2003. Dr. Nikolić received many awards in his career, including the NSF CAREER award in 2003, and the best paper awards at the IEEE International Solid- State Circuits Conference, Symposium on VLSI Circuits, IEEE International SOI Conference, European Solid-State Circuits Research Conference, European Solid-State Device Research Conference, S3S conference and the ACM/IEEE International Symposium of Low- Power Electronics.

Dear All,   Greetings of the day. Thank you for your interest to attend  SSCS DL: Lessons from Brain Connectivity for Fu...
25/09/2015

Dear All,

Greetings of the day. Thank you for your interest to attend SSCS DL: Lessons from Brain Connectivity for Future Interconnect in ICs by Prof. Jan Rabaey@today: 16:00 P.M to 17:00 P.M @ Auditorium, 4th floor , ISEP, 92130, Issy-Les-Moulineaux.

Here is the remainder of the talk. We wish you a great learning and networking experience. Please join us for the cocktail reception after the talk.

Thanks & Regards

ISEP-IEEE Student Branch

21/09/2015
08/09/2015

The ISEP IEEE Student Branch, in association with IEEE CAS France invited you to attend a distinguished lecture from SSCS society on “Lessons from Brain Connectivity for Future Interconnect in ICs” by Prof. Jan Rabaey on Friday, 25th of September 2015 from 16:00 to 17:00. The talk will take place in…

Programming Mobile Applications for Android Handheld Systems: Part 1 (Coursera).... A course of interest for IEEE Moble ...
02/01/2015

Programming Mobile Applications for Android Handheld Systems: Part 1 (Coursera).... A course of interest for IEEE Moble Application Development Contest teams :-)

https://www.mooc-list.com/course/programming-mobile-applications-android-handheld-systems-part-1-coursera?utm_source=MOOC+List+Newsletter&utm_campaign=b307206f15-New_courses_at_MOOC_List_Take_a_look_1_1_2015&utm_medium=email&utm_term=0_c313b4ca1c-b307206f15-232787101

This course provides a comprehensive introduction to the design and implementation of Android applications for handheld systems, such as smartphones and tablets.

29/12/2014

IEEE Moble Application Development Contest

IEEEmadC - Mobile Applications Development Contest for IEEE student members

09/12/2014

Free one-year IEEE Industry Applications Society membership for 2015!

Use promo code: R10IAS2015, in your IEEE cart when you add Industry Applications Society!

Cocktail & Networking:
06/12/2014

Cocktail & Networking:

FiresideChat: Key learnings and advice to launch your hardware startup by Mr. Cedric Giorgi (Head of startup relations S...
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FiresideChat: Key learnings and advice to launch your hardware startup by Mr. Cedric Giorgi (Head of startup relations SigFOX)

Presentation 6: Doing research and innovation in SMEs supported by European framework programmes by Ms. Ingénieur Gloria...
06/12/2014

Presentation 6: Doing research and innovation in SMEs supported by European framework programmes by Ms. Ingénieur Gloria TUQUERRES, IEEE Senior member.

IEEE Entrepreneur Networks: Mr. Costas Stasopoulos...President Elect..IEEE Region 8.
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